Field of the Disclosure
The present disclosure generally relates to designing of integrated circuits, and specifically to reuse of extracted layout-dependent effects (LDE) for circuit design using circuit stencils.
Description of the Related Arts
A design flow for integrated circuits typically includes the steps of transistor-level design and simulation to generate a clean schematic design. The design flow further includes creating a layout for the simulated schematic and running layout-vs-schematic (LVS) checks and design rule checks (DRC) on the layout. LVS refers to determining whether a particular integrated circuit layout corresponds to the original schematic design, while DRC refers to determines whether the physical layout of a particular chip satisfies a series of recommended parameters called design rules. Once the layout is determined to be LVS and DRC clean, layout-dependent effects (LDE) information such as for circuit parasitics (e.g., capacitance of wires) may be extracted from the layout. The LDE information may be back-annotated to the pre-layout schematic, and a re-simulation is performed to determine the impact of the LDE on the design performance. The LDE information extraction, back-annotation, and re-simulation often lead to design changes, which lead to additional layout changes, which in turn lead to more design iterations. This phenomenon becomes worse at smaller geometry processes, where impacts of LDE on integrated circuit designs are higher.